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FCCM
1999
IEEE
134views VLSI» more  FCCM 1999»
15 years 2 months ago
Runlength Compression Techniques for FPGA Configurations
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
Scott Hauck, William D. Wilson
IPPS
2006
IEEE
15 years 4 months ago
Exploiting processing locality through paging configurations in multitasked reconfigurable systems
FPGA chips in reconfigurable computer systems are used as malleable coprocessors where components of a hardware library of functions can be configured as needed. As the number of ...
T. Taher, Tarek A. El-Ghazawi
ICPR
2006
IEEE
15 years 11 months ago
Configuring Mixed Reality Environment
We present a practical framework for registering a Mixed Reality(MR) environment of an arbitrary number of agents. Each agent consist of a head mounted display (HMD), which consis...
Imran N. Junejo, Xiaochun Cao, Hassan Foroosh
ICPADS
2005
IEEE
15 years 3 months ago
A Configurable Time-Controlled Clustering Algorithm for Wireless Sensor Networks
Future large-scale sensor networks may comprise thousands of wirelessly connected sensor nodes that could provide an unimaginable opportunity to interact with physical phenomena i...
S. Selvakennedy, Sukunesan Sinnappan
ASAP
2006
IEEE
138views Hardware» more  ASAP 2006»
15 years 1 months ago
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates. This paper pr...
Marjan Karkooti, Predrag Radosavljevic, Joseph R. ...