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IPPS
2010
IEEE
14 years 8 months ago
Restructuring parallel loops to curb false sharing on multicore architectures
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...
Santosh Sarangkar, Apan Qasem
VLDB
2004
ACM
106views Database» more  VLDB 2004»
15 years 3 months ago
Structures, Semantics and Statistics
At a fundamental level, the key challenge in data integration is to reconcile the semantics of disparate data sets, each expressed with a different database structure. I argue th...
Alon Y. Halevy
89
Voted
IMC
2006
ACM
15 years 4 months ago
Measurement based analysis, modeling, and synthesis of the internet delay space
Understanding the characteristics of the Internet delay space (i.e., the all-pairs set of static round-trip propagation delays among edge networks in the Internet) is important fo...
Bo Zhang, T. S. Eugene Ng, Animesh Nandi, Rudolf H...
ASAP
2006
IEEE
110views Hardware» more  ASAP 2006»
15 years 4 months ago
Loop Transformation Methodologies for Array-Oriented Memory Management
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
Florin Balasa, Per Gunnar Kjeldsberg, Martin Palko...
EMNLP
2009
14 years 8 months ago
Improved Statistical Machine Translation Using Monolingually-Derived Paraphrases
Untranslated words still constitute a major problem for Statistical Machine Translation (SMT), and current SMT systems are limited by the quantity of parallel training texts. Augm...
Yuval Marton, Chris Callison-Burch, Philip Resnik