109 search results - page 4 / 22 » Data cache locking for higher program predictability |
RTAS
2005
IEEE
15 years 3 months ago
2005
IEEE
While caches have become invaluable for higher-end architectures due to their ability to hide, in part, the gap between processor speed and memory access times, caches (and partic...
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ISCA
1995
IEEE
15 years 1 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
IEEEINTERACT
2002
IEEE
15 years 2 months ago
2002
IEEE
Smaller input data sets such as the test and the train input sets are commonly used in simulation to estimate the impact of architecture/micro-architecture features on the perform...
BIRTHDAY
2009
Springer
15 years 2 months ago
2009
Springer
For many aspects of memory theoretical treatment already exists, in particular for: simple cache construction, store buers and store buer forwarding, cache coherence protocols, o...
MICRO
2010
IEEE
14 years 7 months ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...