491 search results - page 36 / 99 » Data communication estimation and reduction for reconfigurab... |
DAC
2001
ACM
16 years 23 days ago
2001
ACM
This paper presents LOTTERYBUS, a novel high-performance communication architecture for system-on-chip (SoC) designs. The LOTTERYBUS architecture was designed to address the follo...
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RSP
1998
IEEE
15 years 4 months ago
1998
IEEE
One of the major differences in partitioning for codesign is in the way the communication cost is evaluated. Generally the size of the edge cut-set is used. When communication bet...
DATE
2010
IEEE
2010
IEEE
An error-correcting unordered code and hardware support for robust asynchronous global communication
15 years 4 months ago
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
ICPP
1999
IEEE
15 years 4 months ago
1999
IEEE
This paper describes a technique called producer-push that enhances the performance of a page-based software distributed shared memory system. Shared data, in software DSM systems...
GLOBECOM
2008
IEEE
15 years 6 months ago
2008
IEEE
— The search for optimality in the design of channel precoders and training symbols in block processing communication systems is one of paramount importance. Finding the best tra...