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DAC
2008
ACM
15 years 11 months ago
Type-matching clock tree for zero skew clock gating
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-...
DAC
2008
ACM
15 years 11 months ago
Daedalus: toward composable multimedia MP-SoC design
Daedalus is a system-level design flow for the design of multiprocessor system-on-chip (MP-SoC) based embedded multimedia systems. It offers a fully integrated tool-flow in which ...
Hristo Nikolov, Mark Thompson, Todor Stefanov, And...
DAC
2007
ACM
15 years 11 months ago
A System For Coarse Grained Memory Protection In Tiny Embedded Processors
Many embedded systems contain resource constrained microcontrollers where applications, operating system components and device drivers reside within a single address space with no...
Ram Kumar, Akhilesh Singhania, Andrew Castner, Edd...
DAC
2003
ACM
15 years 10 months ago
Multilevel floorplanning/placement for large-scale modules using B*-trees
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hanna...
DAC
2006
ACM
15 years 10 months ago
Efficient simulation of critical synchronous dataflow graphs
Simulation and verification using electronic design automation (EDA) tools are key steps in the design process for communication and signal processing systems. The synchronous dat...
Chia-Jui Hsu, José Luis Pino, Ming-Yung Ko,...
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