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» Data partitioning on chip multiprocessors
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MICRO
2010
IEEE
140views Hardware» more  MICRO 2010»
13 years 4 months ago
STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches
Efficient management of last level caches (LLCs) plays an important role in bridging the performance gap between processor cores and main memory. This paper is motivated by two key...
Dongyuan Zhan, Hong Jiang, Sharad C. Seth
MICRO
2010
IEEE
128views Hardware» more  MICRO 2010»
13 years 4 months ago
Adaptive and Speculative Slack Simulations of CMPs on CMPs
Current trends signal an imminent crisis in the simulation of future CMPs (Chip MultiProcessors). Future micro-architectures will offer more and more thread contexts to execute pa...
Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong, ...
BMCBI
2010
185views more  BMCBI 2010»
13 years 1 months ago
MetaPIGA v2.0: maximum likelihood large phylogeny estimation using the metapopulation genetic algorithm and other stochastic heu
Background: The development, in the last decade, of stochastic heuristics implemented in robust application softwares has made large phylogeny inference a key step in most compara...
Raphaël Helaers, Michel C. Milinkovitch
IEEEPACT
2002
IEEE
13 years 11 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany
SIGARCH
2008
73views more  SIGARCH 2008»
13 years 6 months ago
Servo: a programming model for many-core computing
Conventional programming models were designed to be used by expert programmers for programming for largescale multiprocessors, distributed computational clusters, or specialized p...
Nicolas Zea, John Sartori, Rakesh Kumar