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ICCAD
1995
IEEE
135views Hardware» more  ICCAD 1995»
15 years 3 months ago
An iterative improvement algorithm for low power data path synthesis
We address the problem of minimizing power consumption in behavioral synthesis of data-dominated circuits. The complex nature of power as a cost function implies that the effects ...
Anand Raghunathan, Niraj K. Jha
LREC
2010
173views Education» more  LREC 2010»
15 years 1 months ago
Heterogeneous Data Sources for Signed Language Analysis and Synthesis: The SignCom Project
This paper describes how heterogeneous data sources captured in the SignCom project may be used for the analysis and synthesis of French Sign Language (LSF) utterances. The captur...
Kyle Duarte, Sylvie Gibet
ICCAD
1994
IEEE
104views Hardware» more  ICCAD 1994»
15 years 3 months ago
Module selection and data format conversion for cost-optimal DSP synthesis
In high level synthesis each node of a synchronous dataflow graph (DFG) is scheduled to a specific time and allocated to a processor. In this paper we present new integer linear p...
Kazuhito Ito, Lori E. Lucke, Keshab K. Parhi
92
Voted
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
15 years 4 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim
FDL
2005
IEEE
15 years 5 months ago
Synthesis for Unified Control- and Data-Oriented Models
In the Software/Hardware Engineering model-driven design methodology, preservation of real-time system properties can be guaranteed in the model synthesis up to a small time-deviat...
Oana Florescu, Jeroen Voeten, Henk Corporaal