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ISLPED
1995
ACM
100views Hardware» more  ISLPED 1995»
15 years 3 months ago
Simultaneous scheduling and binding for power minimization during microarchitecture synthesis
ABSTRACT { Sub-micron technologies and the increasing size and complexity of integrated components have aggravated the e ect of long interconnects and buses, compared to that of ga...
Aurobindo Dasgupta, Ramesh Karri
EMMCVPR
2007
Springer
15 years 6 months ago
Bayesian Inference for Layer Representation with Mixed Markov Random Field
Abstract. This paper presents a Bayesian inference algorithm for image layer representation [26], 2.1D sketch [6], with mixed Markov random field. 2.1D sketch is an very important...
Ru-Xin Gao, Tianfu Wu, Song Chun Zhu, Nong Sang
GLVLSI
2007
IEEE
135views VLSI» more  GLVLSI 2007»
15 years 6 months ago
Exact sat-based toffoli network synthesis
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
Daniel Große, Xiaobo Chen, Gerhard W. Dueck,...
ADBIS
2005
Springer
120views Database» more  ADBIS 2005»
15 years 5 months ago
Extensible Canonical Process Model Synthesis Applying Formal Interpretation
The current period of IT development is characterized by an explosive growth of diverse information representation languages. Applying integration and composition of heterogeneous ...
Leonid A. Kalinichenko, Sergey A. Stupnikov, Nikol...
ITC
1994
IEEE
151views Hardware» more  ITC 1994»
15 years 4 months ago
Automated Logic Synthesis of Random-Pattern-Testable Circuits
Previous approaches to designing random pattern testable circuits use post-synthesis test point insertion to eliminate random pattern resistant (r.p.r.) faults. The approach taken...
Nur A. Touba, Edward J. McCluskey