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DSD
2010
IEEE
144views Hardware» more  DSD 2010»
14 years 9 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
CAL
2008
14 years 9 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
SBCCI
2005
ACM
276views VLSI» more  SBCCI 2005»
15 years 3 months ago
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way. Congesti...
Aline Mello, Leonel Tedesco, Ney Calazans, Fernand...
CF
2010
ACM
15 years 24 days ago
Hybrid parallel programming with MPI and unified parallel C
The Message Passing Interface (MPI) is one of the most widely used programming models for parallel computing. However, the amount of memory available to an MPI process is limited ...
James Dinan, Pavan Balaji, Ewing L. Lusk, P. Saday...
DATE
2004
IEEE
158views Hardware» more  DATE 2004»
15 years 1 months ago
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
Srinivasan Murali, Giovanni De Micheli