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ISCAS
2005
IEEE
138views Hardware» more  ISCAS 2005»
15 years 10 months ago
A low spur fractional-N frequency synthesizer architecture
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un-Ku Moo...
SCOPES
2004
Springer
15 years 10 months ago
Instruction Selection for Compilers that Target Architectures with Echo Instructions
Echo Instructions have recently been introduced to allow embedded processors to provide runtime decompression of LZ77-compressed programs at a minimal hardware cost compared to oth...
Philip Brisk, Ani Nahapetian, Majid Sarrafzadeh
ISCAS
2003
IEEE
112views Hardware» more  ISCAS 2003»
15 years 10 months ago
Architectures for function evaluation on FPGAs
This paper presents a new family of architectures for multi-cycle area-efficient evaluation of elementary and composite functions, and an exploration of the design tradeoffs for i...
Nalin Sidahao, George A. Constantinides, Peter Y. ...
FPGA
1999
ACM
130views FPGA» more  FPGA 1999»
15 years 9 months ago
Hybrid Product Term and LUT Based Architectures Using Embedded Memory Blocks
The Embedded System Block (ESB) of the APEX20K programmable logic device family from Altera Corporation includes the capability of implementing product term macrocells in addition...
Frank Heile, Andrew Leaver
ERSA
2006
282views Hardware» more  ERSA 2006»
15 years 6 months ago
SyCERS: a SystemC Design Exploration Framework for SoC Reconfigurable Architecture
Reconfigurable devices, such as FPGAs, introduce into the design workflow of embedded systems a new degree of freedom: the designer can have the system autonomously modify the fun...
Carlo Amicucci, Fabrizio Ferrandi, Marco D. Santam...