1602 search results - page 105 / 321 » Database Architectures for New Hardware |
131
Voted
APCCAS
2006
IEEE
15 years 8 months ago
2006
IEEE
in this paper, a new CAVLC decoding architecture with a soft-input design concept is proposed. We introduce the soft-decision information to localize the erroneous position at macr...
111
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ASPDAC
2001
ACM
15 years 8 months ago
2001
ACM
Abstract-- We are proposing "PPRAM-Link": a new highspeed communication standard for merged-DRAM/logic SoC architecture. PPRAM-Link standard is composed of physical/logic...
136
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VTS
1995
IEEE
15 years 8 months ago
1995
IEEE
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
175
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CDES
2010
15 years 3 months ago
2010
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
152
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PDSE
2000
15 years 6 months ago
2000
This work presents a flexible, CORBA compliant Middle-Tier Server architecture which is capable of adding dependability (namely, reliability, availability, and performability) to ...