Sciweavers

1602 search results - page 106 / 321
» Database Architectures for New Hardware
Sort
View
FPL
2009
Springer
100views Hardware» more  FPL 2009»
15 years 8 months ago
A virus scanning engine using a parallel finite-input memory machine and MPUs
This paper presents a virus scanning engine. After showing the difference between ClamAV (an anti-virus software) and SNORT (an intrusion detection software), we show a new archit...
Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura,...
ICSE
1995
IEEE-ACM
15 years 8 months ago
Architectural Mismatch or Why It's Hard to Build Systems Out Of Existing Parts
Many would argue that future breakthroughs in software productivity will dependon our ability to combine existing pieces of software to produce new applications. An important step...
David Garlan, Robert Allen, John Ockerbloom
FCCM
2003
IEEE
135views VLSI» more  FCCM 2003»
15 years 10 months ago
Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable
Hybrid architectures, which are composed of a conventional processor closely coupled with reconfigurable logic, seem to combine the advantages of both types of hardware. They pres...
Benjamin A. Levine, Herman Schmit
136
Voted
ICCD
2002
IEEE
122views Hardware» more  ICCD 2002»
16 years 1 months ago
Using Offline and Online BIST to Improve System Dependability - The TTPC-C Example
Fault-tolerant distributed real-time systems are presently facing a lot of new challenges. Although many techniques provide effective masking of node failures on the architectural...
Andreas Steininger, Johann Vilanek
ICCAD
2006
IEEE
125views Hardware» more  ICCAD 2006»
16 years 1 months ago
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
This paper presents a new Multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: A predictible downward network based on the But...
Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Ha...