Sciweavers

1602 search results - page 118 / 321
» Database Architectures for New Hardware
Sort
View
DATE
2010
IEEE
155views Hardware» more  DATE 2010»
15 years 9 months ago
Bitstream processing for embedded systems using C++ metaprogramming
—This paper suggests a new approach for bitstream processing of embedded systems, using a combination of C++ metaprogramming combined with architecture extensions of an customiza...
Reimund Klemm, Gerhard Fettweis
146
Voted
APCSAC
2001
IEEE
15 years 8 months ago
High-Performance Extendable Instruction Set Computing
In this paper, a new architecture called the extendable instruction set computer (EISC) is introduced that addresses the issues of memory size and performance in embedded micropro...
Heui Lee, Paul Becket, Bill Appelbe
FPGA
2005
ACM
90views FPGA» more  FPGA 2005»
15 years 10 months ago
Using bus-based connections to improve field-programmable gate array density for implementing datapath circuits
Abstract—As the logic capacity of field-programmable gate arrays (FPGAs) increases, they are increasingly being used to implement large arithmetic-intensive applications, which ...
Andy Gean Ye, Jonathan Rose
EXPCS
2007
15 years 8 months ago
RiceNIC: a reconfigurable network interface for experimental research and education
The evaluation of new network server architectures is usually performed experimentally using either a simulator or a hardware prototype. Accurate simulation of the hardwaresoftwar...
Jeffrey Shafer, Scott Rixner
SIGMETRICS
2010
ACM
213views Hardware» more  SIGMETRICS 2010»
15 years 9 months ago
Small subset queries and bloom filters using ternary associative memories, with applications
Associative memories offer high levels of parallelism in matching a query against stored entries. We design and analyze an architecture which uses a single lookup into a Ternary C...
Ashish Goel, Pankaj Gupta