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ISCAS
2008
IEEE
89views Hardware» more  ISCAS 2008»
15 years 11 months ago
Multi-loop efficient sturdy MASH delta-sigma modulators
— An extended version of sturdy MASH delta-sigma modulators is presented in this paper. Improved performance is achieved using in-band zero optimization. The challenges towards h...
Nima Maghari, Un-Ku Moon
DATE
2007
IEEE
91views Hardware» more  DATE 2007»
15 years 11 months ago
Remote testing and diagnosis of System-on-Chips using network management frameworks
This paper presents a new approach that allows remote testing and diagnosis of complex (Systems-on-Chip) and embedded IP cores. The approach extends both on-chip design-for-test (...
Oussama Laouamri, Chouki Aktouf
161
Voted
ITC
2003
IEEE
138views Hardware» more  ITC 2003»
15 years 10 months ago
Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
Yannick Bonhomme, Patrick Girard, Loïs Guille...
117
Voted
DATE
2002
IEEE
138views Hardware» more  DATE 2002»
15 years 10 months ago
Automatic Evaluation of the Accuracy of Fixed-Point Algorithms
The minimization of cost, power consumption and timeto-market of DSP applications requires the development of methodologies for the automatic implementation of floating-point alg...
Daniel Menard, Olivier Sentieys
DATE
2000
IEEE
137views Hardware» more  DATE 2000»
15 years 9 months ago
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
Stefan Pees, Andreas Hoffmann, Heinrich Meyr