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ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 1 months ago
Performance Efficiency of Context-Flow System-on-Chip Platform
Recent efforts in adapting computer networks into system-on-chip (SOC), or network-on-chip, present a setback to the traditional computer systems for the lack of effective program...
Rami Beidas, Jianwen Zhu
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
15 years 11 months ago
Wire Sizing Alternative - An Uniform Dual-rail Routing Architecture
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
Fu-Wei Chen, Yi-Yu Liu
ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
15 years 10 months ago
Enhanced Architectural Support for Variable-Length Decoding
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
Mohanarajah Sinnathamby, Subramania Sudharsanan, N...
ISCA
2003
IEEE
112views Hardware» more  ISCA 2003»
15 years 9 months ago
A Pipelined Memory Architecture for High Throughput Network Processors
Designing ASICs for each new generation of backbone routers is a time intensive and fiscally draining process. In this paper we focus on the design of a programmable architecture...
Timothy Sherwood, George Varghese, Brad Calder
CODES
2002
IEEE
15 years 9 months ago
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures
Dynamic run-time scheduling in System-on-Chip platforms has become recently an active area of research because of the performance and power requirements of new applications. Moreo...
Juanjo Noguera, Rosa M. Badia