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» Dataflow Architectures for GALS
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HIPEAC
2009
Springer
15 years 3 months ago
HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic
Abstract. Exposing more instruction-level parallelism in out-of-order superscalar processors requires increasing the number of dynamic in-flight instructions. However, large instru...
Suriya Subramanian, Kathryn S. McKinley
EUROSYS
2010
ACM
15 years 5 months ago
PUSH: A Dataflow Shell
The deluge of huge data sets such as those provided by sensor networks, online transactions, and the web provide exciting opportunities for data analysis. The scale of the data ...
Noah Evans, Eric Van Hensbergen
MICRO
2008
IEEE
79views Hardware» more  MICRO 2008»
14 years 11 months ago
Strategies for mapping dataflow blocks to distributed hardware
Distributed processors must balance communication and concurrency. When dividing instructions among the processors, key factors are the available concurrency, criticality of depen...
Behnam Robatmili, Katherine E. Coons, Doug Burger,...
HOTOS
2009
IEEE
15 years 3 months ago
FLUXO: A Simple Service Compiler
In this paper, we propose FLUXO, a system that separates an Internet service's logical functionality from the architectural decisions made to support performance, scalability...
Emre Kiciman, V. Benjamin Livshits, Madanlal Musuv...
DATE
2008
IEEE
121views Hardware» more  DATE 2008»
15 years 6 months ago
Quantitative Evaluation in Embedded System Design: Validation of Multiprocessor Multithreaded Architectures
As levels of parallelism are becoming increasingly complex in multiprocessor architectures, GALS, and asynchronous circuits, methodologies and software tools are needed to verify ...
Nicolas Coste, Hubert Garavel, Holger Hermanns, Ri...