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» Dataflow Architectures for GALS
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CODES
1998
IEEE
15 years 4 months ago
The construction of a retargetable simulator for an architecture template
Systems in the domain of high-performance video signal processing are becoming more and more programmable. We suggest an approach to design such systems that involves measuring, v...
Bart Kienhuis, Ed F. Deprettere, Kees A. Vissers, ...
MEMOCODE
2008
IEEE
15 years 6 months ago
Virtual prototyping AADL architectures in a polychronous model of computation
While synchrony and asynchrony are two distinct concepts of concurrency theory, effective and formally defined embedded system design methodologies usually mix the best from both...
Ma Yue, Jean-Pierre Talpin, Thierry Gautier
ICRA
2007
IEEE
117views Robotics» more  ICRA 2007»
15 years 6 months ago
Integration of Coordination Mechanisms in the BITE Multi-Robot Architecture
— Recent years are seeing a renewed interest in general multi-robot architectures, capable of automating coordination. However, few architectures explore integration of multiple ...
Gal A. Kaminka, Inna Frenkel
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
15 years 5 months ago
Application adaptive energy efficient clustered architectures
As clock frequency and die area increase, achieving energy efficiency, while distributing a low skew, global clock signal becomes increasingly difficult. Challenges imposed by dee...
Diana Marculescu
VLSISP
2008
129views more  VLSISP 2008»
14 years 11 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...