Sciweavers

165 search results - page 29 / 33
» Dataflow Architectures for GALS
Sort
View
HPCA
2008
IEEE
16 years 1 days ago
Fundamental performance constraints in horizontal fusion of in-order cores
A conceptually appealing approach to supporting a broad range of workloads is a system comprising many small cores that can be fused, on demand, into larger cores. We demonstrate ...
Pierre Salverda, Craig B. Zilles
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 4 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ICIP
2007
IEEE
16 years 1 months ago
GPS, GIS and Video Registration for Building Reconstruction
3D reconstruction of urban environments is a widely studied subject since several years, as it can lead to many useful applications: virtual navigation, augmented reality, archite...
Gaël Sourimant, Kadi Bouatouch, Luce Morin
DAC
2009
ACM
16 years 20 days ago
Enabling adaptability through elastic clocks
Power and performance benefits of scaling are lost to worst case margins as uncertainty of device characteristics is increasing. Adaptive techniques can dynamically adjust the mar...
Emre Tuncer, Jordi Cortadella, Luciano Lavagno
90
Voted
CISIS
2008
IEEE
15 years 1 months ago
Multi-variant Program Execution: Using Multi-core Systems to Defuse Buffer-Overflow Vulnerabilities
While memory-safe and type-safe languages have been available for many years, the vast majority of software is still implemented in type-unsafe languages such as C/C++. Despite ma...
Babak Salamat, Andreas Gal, Todd Jackson, Karthike...