165 search results - page 3 / 33 » Dataflow Architectures for GALS |
102
Voted
ASYNC
2006
IEEE
15 years 9 months ago
2006
IEEE
161
Voted
APCSAC
2000
IEEE
15 years 7 months ago
2000
IEEE
Dataflow computation models enable simpler and more efficient management of the memory hierarchy - a key barrier to the performance of many parallel programs. This paper describes...
135
Voted
ISVLSI
2008
IEEE
15 years 10 months ago
2008
IEEE
The evolution of deep submicron technologies allows the development of increasingly complex Systems on a Chip (SoC). However, this evolution is rendering less viable some well-est...
129
Voted
CGF
2010
15 years 3 months ago
2010
We propose a new framework design for exploiting multi-core architectures in the context of visualization dataflow systems. Recent hardware advancements have greatly increased the...
122
Voted
ENTCS
2006
15 years 3 months ago
2006
In recent years several successful GALS realizations have been presented. The core of a GALS system is a locally synchronous island that is designed using industry standard synchr...