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» Dataflow Architectures for GALS

152

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CODES
2005
IEEE

92views Software Engineering» more CODES 2005»

Designing real-time H.264 decoders with dataflow architectures

15 years 11 months ago

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High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...

Youngsoo Kim, Suleyman Sair

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178

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JUCS
2000

120views more JUCS 2000»

Execution and Cache Performance of the Scheduled Dataflow Architecture

15 years 5 months ago

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: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...

Krishna M. Kavi, Joseph Arul, Roberto Giorgi

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155

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ISCA
2006
IEEE

130views Hardware» more ISCA 2006»

Area-Performance Trade-offs in Tiled Dataflow Architectures

15 years 5 months ago

Download wavescalar.cs.washington.edu

: Tiled architectures, such as RAW, SmartMemories, TRIPS, and WaveScalar, promise to address several issues facing conventional processors, including complexity, wire-delay, and pe...

Steven Swanson, Andrew Putnam, Martha Mercaldi, Ke...

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111

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HIPEAC
2009
Springer

109views System Software» more HIPEAC 2009»

Compiler Controlled Speculation for Power Aware ILP Extraction in Dataflow Architectures

16 years 11 days ago