145 search results - page 11 / 29 » Datapath Scheduling using Dynamic Frequency Clocking |
ISCAS
2008
IEEE
15 years 3 months ago
2008
IEEE
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
111
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FAST
2004
14 years 11 months ago
2004
CLOCK is a classical cache replacement policy dating back to 1968 that was proposed as a low-complexity approximation to LRU. On every cache hit, the policy LRU needs to move the a...
77
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ASYNC
2000
IEEE
15 years 1 months ago
2000
IEEE
Self-timed systems often have to communicate with their environment through a clocked interface. For example, off-chip memory may require clocking and this can reduce the benefit...
ISQED
2007
IEEE
15 years 3 months ago
2007
IEEE
In high-level synthesis for FPGA designs, scheduling and chaining of operations for optimal performance remain challenging problems. In this paper, we present a balanced schedulin...