145 search results - page 12 / 29 » Datapath Scheduling using Dynamic Frequency Clocking |
ARC
2006
Springer
15 years 1 months ago
2006
Springer
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
MICRO
2008
IEEE
15 years 3 months ago
2008
IEEE
Any architectural optimization aims at satisfying the end user. However, modern architectures execute with little to no knowledge about the individual user. If architectures could...
ERSA
2008
14 years 11 months ago
2008
Coarse-grained dynamically reconfigurable processor arrays (DRPAs) have been received an attention as a flexible and efficient off-loading engine for various types of System-on-Ch...
VLSID
2007
IEEE
15 years 10 months ago
2007
IEEE
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
ICCAD
2002
IEEE
15 years 6 months ago
2002
IEEE
Dynamic voltage scaling (DVS) reduces the power consumption of processors when peak performance is unnecessary. However, the achievable power savings by DVS alone is becoming limi...