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DATE
1998
IEEE
116views Hardware» more  DATE 1998»
15 years 10 months ago
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform
This paper presents a VLSI Architecture to implement the forward and inverse 2-D Discrete Wavelet Transform (FDWT/IDWT), to compress medical images for storage and retrieval. Loss...
Isidoro Urriza, José I. Artigas, José...
DATE
2007
IEEE
141views Hardware» more  DATE 2007»
15 years 10 months ago
Energy-efficient real-time task scheduling with task rejection
In the past decade, energy-efficiency has been an important system design issue in both hardware and software managements. For mobile applications with critical missions, both ene...
Jian-Jia Chen, Tei-Wei Kuo, Chia-Lin Yang, Ku-Jei ...
DATE
2004
IEEE
121views Hardware» more  DATE 2004»
15 years 10 months ago
Experiences during the Experimental Validation of the Time-Triggered Architecture
During last years, the Time-Triggered Architecture (TTA) has been gaining acceptance as a generic architecture for highly dependable real-time systems. It is now being used to imp...
Sara Blanc, Joaquin Gracia, Pedro J. Gil
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 10 months ago
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach
Future Systems-on-Chips will include multiple heterogeneous processing units, with complex data-dependent shared resource access patterns dictating the performance of a design. Cu...
Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, ...
DATE
2004
IEEE
154views Hardware» more  DATE 2004»
15 years 10 months ago
MultiNoC: A Multiprocessing System Enabled by a Network on Chip
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
Aline Mello, Leandro Möller, Ney Calazans, Fe...