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» Decoupled Hardware Support for Distributed Shared Memory
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HPCA
2011
IEEE
14 years 3 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
ICPP
2003
IEEE
15 years 5 months ago
Enabling Partial Cache Line Prefetching Through Data Compression
Hardware prefetching is a simple and effective technique for hiding cache miss latency and thus improving the overall performance. However, it comes with addition of prefetch buff...
Youtao Zhang, Rajiv Gupta
HPCA
2011
IEEE
14 years 3 months ago
MOPED: Orchestrating interprocess message data on CMPs
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Su...
ASAP
2007
IEEE
135views Hardware» more  ASAP 2007»
15 years 6 months ago
An Application Specific Memory Characterization Technique for Co-processor Accelerators
Commodity accelerator technologies including reconfigurable devices provide an order of magnitude performance improvement compared to mainstream microprocessor systems. A number o...
Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith
SIGOPSE
1996
ACM
15 years 4 months ago
How to scale transactional storage systems
Applications of the future will need to support large numbers of clients and will require scalable storage systems that allow state to be shared reliably. Recent research in distr...
Liuba Shrira, Barbara Liskov, Miguel Castro, Atul ...