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80
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FPL
2009
Springer
102views Hardware» more  FPL 2009»
15 years 5 months ago
Macs: A Minimal Adaptive routing circuit-switched architecture for scalable and parametric NoCs
Networks-on-Chips (NoCs) are an emerging communication topology paradigm in single chip VLSI design, enhancing parallelism and system scalability. Processing units (PUs) connect t...
Rohit Kumar, Ann Gordon-Ross
FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 5 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
102
Voted
FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 5 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
FPL
2009
Springer
113views Hardware» more  FPL 2009»
15 years 5 months ago
Static versus scheduled interconnect in Coarse-Grained Reconfigurable Arrays
Spatially-tiled architectures, such as Coarse-Grained Reconfigurable Arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, em...
Brian Van Essen, Aaron Wood, Allan Carroll, Stephe...
100
Voted
GI
2009
Springer
15 years 5 months ago
NeuroQLab - A Software Assistant for Neurosurgical Planning and Quantitative Image Analysis
Neuroimaging techniques produce large amounts of data capable of displaying a wide variety of structural and functional properties of the brain. A large number of specialized image...
Florian Weiler, Jan Rexilius, Jan Klein, Horst K. ...