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ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
15 years 2 months ago
Test pattern generation for width compression in BIST
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
Paulo F. Flores, Horácio C. Neto, K. Chakra...
IEAAIE
1999
Springer
15 years 2 months ago
The Design of a Multi-tiered Bus Timetabling System
This paper describes the design of the Bus Timetabling System (BTS) we have developed for one of the largest privately held bus companies in the world. This Bus Company operates cl...
Andy Hon Wai Chun, Steve Ho Chuen Chan
IPPS
1998
IEEE
15 years 2 months ago
Code Transformations for Low Power Caching in Embedded Multimedia Processors
In this paper, we present several novel strategies to improve software controlled cache utilization, so as to achieve lower power requirements for multi-media and signal processin...
Chidamber Kulkarni, Francky Catthoor, Hugo De Man
ASPDAC
1998
ACM
81views Hardware» more  ASPDAC 1998»
15 years 2 months ago
A Heuristic Algorithm to Design AND-OR-EXOR Three-Level Networks
—An AND-OR-EXOR network, where the output EXOR gate has only two inputs, is one of the simplest three-level architecture. This network realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
INFOCOM
1997
IEEE
15 years 2 months ago
Restoration Strategies and Spare Capacity Requirements in Self-Healing ATM Networks
—This paper studies the capacity and flow assignment problem arising in the design of self-healing asynchronous transfer mode (ATM) networks using the virtual path concept. The ...
Yijun Xiong, Lorne Mason