10 search results - page 2 / 2 » Defect Tolerance for Nanoscale Crossbar-Based Devices |
VLSID
2004
IEEE
16 years 5 hour ago
2004
IEEE
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
117
Voted
MICRO
2006
IEEE
14 years 11 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
85
Voted
TCAD
2008
14 years 11 months ago
2008
Abstract--The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) deco...
DAC
2005
ACM
16 years 18 days ago
2005
ACM
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
95
Voted
DAC
2005
ACM
16 years 18 days ago
2005
ACM
Device and interconnect fabrics at the nanoscale will have a density of defects and susceptibility to transient faults far exceeding those of current silicon technologies. In this...