41 search results - page 3 / 9 » Defect Tolerance in Multiple-FPGA Systems |
99
Voted
ICCD
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume lit...
106
Voted
CASES
2009
ACM
15 years 4 months ago
2009
ACM
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
136
Voted
SRDS
2010
IEEE
14 years 11 months ago
2010
IEEE
Data aggregation scheduling, or convergecast, is a fundamental pattern of communication in wireless sensor networks (WSNs), where sensor nodes aggregate and relay data to a sink no...
96
Voted
ISCA
2010
IEEE
15 years 6 months ago
2010
IEEE
Aggressive technology scaling into the nanometer regime has led to a host of reliability challenges in the last several years. Unlike onchip caches, which can be efficiently prot...
90
Voted
DFT
2005
IEEE
15 years 6 months ago
2005
IEEE
Detection of defective pixels that develop on-line is a vital part of fault tolerant schemes for repairing imagers during operation. This paper presents a new algorithm for the id...