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FPGA
2006
ACM
125views FPGA» more  FPGA 2006»
15 years 9 months ago
Armada: timing-driven pipeline-aware routing for FPGAs
While previous research has shown that FPGAs can efficiently implement many types of computations, their flexibility inherently limits their clock rate. Several research groups ha...
Kenneth Eguro, Scott Hauck
157
Voted
HPCA
1995
IEEE
15 years 9 months ago
Reducing Communication Latency with Path Multiplexing in Optically Interconnected Multiprocessor Systems
—Reducing communication latency, which is a performance bottleneck in optically interconnected multiprocessor systems, is of prominent importance. A conventional approach for est...
Chunming Qiao, Rami G. Melhem
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 9 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
CCS
2008
ACM
15 years 7 months ago
Dependent link padding algorithms for low latency anonymity systems
Low latency anonymity systems are susceptive to traffic analysis attacks. In this paper, we propose a dependent link padding scheme to protect anonymity systems from traffic analy...
Wei Wang 0002, Mehul Motani, Vikram Srinivasan
CDC
2008
IEEE
186views Control Systems» more  CDC 2008»
15 years 7 months ago
A mathematical model of the Skype VoIP congestion control algorithm
The Internet is changing from being only an efficient platform for data delivery to become also a platform for audio/video applications. The stability of the traditional Internet i...
Luca De Cicco, Saverio Mascolo, Vittorio Palmisano