138 search results - page 11 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
ASYNC
2002
IEEE
15 years 4 months ago
2002
IEEE
Advanced clock-delayed1 and self-resetting domino circuits are becoming increasingly important design styles in aggressive synchronous as well as asynchronous design. Their design...
ICCAD
2008
IEEE
15 years 8 months ago
2008
IEEE
Statistical static timing analysis (SSTA) has emerged as an essential tool for nanoscale designs. Monte Carlo methods are universally employed to validate the accuracy of the appr...
GLVLSI
2006
IEEE
15 years 5 months ago
2006
IEEE
Process variations have become a key concern of circuit designers because of their significant, yet hard to predict impact on performance and signal integrity of VLSI circuits. St...
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ICCAD
2007
IEEE
15 years 6 months ago
2007
IEEE
Modeling the effect of coupling noise on circuit delay is a key issue in static timing analysis (STA) and involves the “victimaggressor alignment” problem. As delay-noise depe...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
A physical yet compact gate delay model is developed integrating short-channel effects and the Alpha-power law based timing model. This analytical approach accurately predicts bot...