138 search results - page 14 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
DAC
2005
ACM
15 years 1 months ago
2005
ACM
We present an efficient and accurate gate sizing tool that employs a novel piecewise convex delay model, handling both rise and fall delays, for static CMOS gates. The delay model...
79
Voted
DAC
2000
ACM
15 years 4 months ago
2000
ACM
: The impact of coupling capacitance on delay is usually estimated by scaling the coupling capacitances (often by a factor of 2) and modeling them as grounded. This simple approach...
92
Voted
ICCAD
2001
IEEE
15 years 8 months ago
2001
IEEE
We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simu...
99
Voted
DAC
2004
ACM
15 years 3 months ago
2004
ACM
There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assum...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new lat...