138 search results - page 19 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Recently there has been considerable interest in incorporating timing effects of microarchitectural features of processors (e.g. caches and pipelines) into the schedulability anal...
PDP
2009
IEEE
15 years 6 months ago
2009
IEEE
Existing approaches for modelling the Internet delay space predict end-to-end delays between two arbitrary hosts as static values. Further, they do not capture the characteristics...
DATE
2006
IEEE
15 years 5 months ago
2006
IEEE
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
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VTS
2000
IEEE
15 years 4 months ago
2000
IEEE
The performance of deep sub-micron designs can be affected by various parametric variations, manufacturing defects, noise or even modeling errors that are all statistical in natur...
DAC
2003
ACM
16 years 18 days ago
2003
ACM
Noise affects circuit operation by increasing gate delays and causing latches to capture incorrect values. This paper proposes a method of characterizing correlation of signal tra...