138 search results - page 6 / 28 » Delay modeling and static timing analysis for MTCMOS circuit... |
125
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TCAD
2008
14 years 11 months ago
2008
Manufacturing process variations lead to variability in circuit delay and, if not accounted for, can cause excessive timing yield loss. The familiar traditional approaches to timin...
88
Voted
ISPD
2003
ACM
15 years 4 months ago
2003
ACM
We propose a method to capture crosstalk-induced noisy waveform for crosstalk-aware static timing analysis. The effects of capacitive coupling noise on timing are conventionally m...
ICCAD
1999
IEEE
15 years 3 months ago
1999
IEEE
Partially depleted silicon-on-insulator (PD-SOI) has emerged as a technology of choice for high-performance low-power deep-submicrometer digital integrated circuits. An important c...
85
Voted
VLSID
2002
IEEE
16 years 4 hour ago
2002
IEEE
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
82
Voted
FPGA
2007
ACM
15 years 5 months ago
2007
ACM
Variations in the semiconductor fabrication process results in variability in parameters between transistors on the same die, a problem exacerbated by lithographic scaling. The re...