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» Delay variation tolerance for domino circuits
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ASPDAC
2009
ACM
122views Hardware» more  ASPDAC 2009»
14 years 26 days ago
Tolerating process variations in high-level synthesis using transparent latches
—Considering process variability at the behavior synthesis level is necessary, because it makes some instances of function units slower and others faster, resulting in unbalanced...
Yibo Chen, Yuan Xie
ISLPED
2006
ACM
129views Hardware» more  ISLPED 2006»
14 years 9 days ago
Variation-driven device sizing for minimum energy sub-threshold circuits
Sub-threshold operation is a compelling approach for energyconstrained applications, but increased sensitivity to variation must be mitigated. We explore variability metrics and t...
Joyce Kwong, Anantha P. Chandrakasan
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
13 years 11 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
ACSD
2009
IEEE
100views Hardware» more  ACSD 2009»
14 years 1 months ago
Scheduling Synchronous Elastic Designs
Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility ...
Josep Carmona, Jorge Júlvez, Jordi Cortadel...
PATMOS
2007
Springer
14 years 14 days ago
A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
Abstract. The continuous miniaturization of semiconductor devices imposes serious threats to design robustness against process variations and environmental fluctuations. Modern ci...
Chin-Hsiung Hsu, Szu-Jui Chou, Jie-Hong Roland Jia...