25 search results - page 5 / 5 » Delay variation tolerance for domino circuits |
ASYNC
2007
IEEE
14 years 17 days ago
2007
IEEE
A high data rate asynchronous bit-serial link for long-range on-chip communication is presented. The data bit cycle time is equal to a single gate delay, enabling 67Gbps throughpu...
MEMOCODE
2010
IEEE
13 years 4 months ago
2010
IEEE
Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new corr...
TVLSI
2010
13 years 28 days ago
2010
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
VLSID
2003
IEEE
14 years 6 months ago
2003
IEEE
In this paper we present statistical timing driven hMetisbased partitioning. We approach timing driven partitioning from a different perspective: we use the statistical timing cri...
ISQED
2007
IEEE
14 years 15 days ago
2007
IEEE
With its advantages in wirelength reduction and routing flexibility compared with Manhattan routing, X-architecture has been proposed and applied to modern IC design. As a critic...