38 search results - page 5 / 8 » Delay-Insensitive Ternary Logic |
ISMVL
2003
IEEE
15 years 2 months ago
2003
IEEE
This paper introduces the implementation of the Iterative Symmetry Indices Decomposition (ISID) for the synthesis of ternary threedimensional logic circuits. The synthesis of regu...
ASPDAC
1999
ACM
15 years 1 months ago
1999
ACM
90
Voted
DDECS
2008
IEEE
15 years 4 months ago
2008
IEEE
: We propose a simple and fast two-level minimization algorithm for completely specified functions in this paper. The algorithm is based on processing ternary trees. A ternary tree...
INFOCOM
2012
IEEE
13 years 1 days ago
2012
IEEE
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
80
Voted
FPGA
2008
ACM
14 years 11 months ago
2008
ACM
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...