107 search results - page 6 / 22 » Demonstration of an Automated Control Synthesis Tool for Man... |
CODES
2005
IEEE
15 years 3 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
SIGSOFT
2005
ACM
15 years 10 months ago
2005
ACM
A way of combining object-oriented and structural paradigms of software composition is demonstrated in a tool for generative programming. Metaclasses are introduced that are compon...
DAC
2008
ACM
15 years 10 months ago
2008
ACM
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions un...
VLSID
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract— This paper introduces a fuzzy logic based guidance architecture to a graph grammar framework for automated design of analog circuits. The grammar generates circuit topo...
244
click to vote
DAC
2012
ACM
13 years 1 days ago
2012
ACM
Loop pipelining is a critical transformation in behavioral synthesis. It is crucial to producing hardware designs with acceptable latency and throughput. However, it is a complex ...