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CJ
2006
84views more  CJ 2006»
15 years 4 months ago
Instruction Level Parallelism through Microthreading - A Scalable Approach to Chip Multiprocessors
Most microprocessor chips today use an out-of-order instruction execution mechanism. This mechanism allows superscalar processors to extract reasonably high levels of instruction ...
Kostas Bousias, Nabil Hasasneh, Chris R. Jesshope
131
Voted
EDOC
2002
IEEE
15 years 9 months ago
Model-Based Risk Assessment to Improve Enterprise Security
The main objective of the CORAS project is to provide methods and tools for precise, unambiguous, and efficient risk assessment of security critical systems. To this end, we advoc...
Jan Øyvind Aagedal, Folker den Braber, Theo...
144
Voted
PERCOM
2003
ACM
16 years 4 months ago
Dynamic Bandwidth Management for Single-Hop Ad Hoc Wireless Networks
Distributed weighted fair scheduling schemes for QoS support in wireless networks have not yet become standard. In this paper we propose an Admission Control and Dynamic Bandwidth...
Samarth H. Shah, Kai Chen, Klara Nahrstedt
145
Voted
ICFP
2009
ACM
15 years 11 months ago
Finding race conditions in Erlang with QuickCheck and PULSE
We address the problem of testing and debugging concurrent, distributed Erlang applications. In concurrent programs, race conditions are a common class of bugs and are very hard t...
Koen Claessen, Michal Palka, Nicholas Smallbone, J...
CCGRID
2009
IEEE
15 years 11 months ago
Performance under Failures of DAG-based Parallel Computing
— As the scale and complexity of parallel systems continue to grow, failures become more and more an inevitable fact for solving large-scale applications. In this research, we pr...
Hui Jin, Xian-He Sun, Ziming Zheng, Zhiling Lan, B...