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112
Voted
ISCAS
2007
IEEE
173views Hardware» more  ISCAS 2007»
15 years 8 months ago
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM
— Due to continuous technology scaling, the reduction of nodal capacitances and the lowering of power supply voltages result in an ever decreasing minimal charge capable of upset...
Riaz Naseer, Younes Boulghassoul, Jeff Draper, San...
121
Voted
PRDC
2006
IEEE
15 years 7 months ago
Detecting and Exploiting Symmetry in Discrete-state Markov Models
Dependable systems are usually designed with multiple instances of components or logical processes, and often possess symmetries that may be exploited in model-based evaluation. T...
W. Douglas Obal II, Michael G. McQuinn, William H....
108
Voted
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
15 years 7 months ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
104
Voted
ICS
2004
Tsinghua U.
15 years 7 months ago
Cluster prefetch: tolerating on-chip wire delays in clustered microarchitectures
The growing dominance of wire delays at future technology points renders a microprocessor communication-bound. Clustered microarchitectures allow most dependence chains to execute...
Rajeev Balasubramonian
123
Voted
ATS
2003
IEEE
110views Hardware» more  ATS 2003»
15 years 7 months ago
Chip-Level Diagnostic Strategy for Full-Scan Designs with Multiple Faults
Fault diagnosis of full-scan designs has been progressed significantly. However, most existing techniques are aimed at a logic block with a single fault. Strategies on top of thes...
Yu-Chiun Lin, Shi-Yu Huang