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» Describing Process Patterns with UML
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ATS
2009
IEEE
99views Hardware» more  ATS 2009»
15 years 10 months ago
Test Generation for Designs with On-Chip Clock Generators
High performance designs often use the on-chip device PLLs for accurate test clock generation during testing. The on-chip clock generator is designed in a programmable way to faci...
Xijiang Lin, Mark Kassab
ISCAS
2007
IEEE
128views Hardware» more  ISCAS 2007»
15 years 9 months ago
SAT-based ATPG for Path Delay Faults in Sequential Circuits
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
Stephan Eggersglüß, Görschwin Fey,...
ERLANG
2006
ACM
15 years 9 months ago
From HTTP to HTML: Erlang/OTP experiences in web based service applications
This paper describes the lessons learnt when internally developing web applications in Erlang. On the basis of these experiences, a framework called the Web Platform has been impl...
Francesco Cesarini, Lukas Larsson, Michal Slaski
SGAI
2004
Springer
15 years 8 months ago
Modelling Shared Extended Mind and Collective Representational Content
Some types of animals exploit the external environment to support their cognitive processes, in the sense of patterns created in the environment that function as external mental s...
Tibor Bosse, Catholijn M. Jonker, Martijn C. Schut...
RE
2001
Springer
15 years 7 months ago
Domain Independent Regularities in Scenarios
Scenario is a description technique which has attracted much attention not only from practitioners but also from researchers. Literature on this topic shows the possibilities that...
Marcela Ridao, Jorge Horacio Doorn, Julio Cesar Sa...