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128
Voted
JSA
2010
14 years 7 months ago
2010
The high chip-level integration enables the implementation of large-scale parallel processing architectures with 64 and more processing nodes on a single chip or on an FPGA device...
122
Voted
TMM
2010
14 years 7 months ago
2010
Based on the local keypoints extracted as salient image patches, an image can be described as a "bag-of-visualwords (BoW)" and this representation has appeared promising ...
124
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TMM
2010
14 years 7 months ago
2010
As digital cameras with Global Positioning System (GPS) capability become available and people geotag their photos using other means, it is of great interest to annotate semantic e...
149
Voted
TVLSI
2010
14 years 7 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
125
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ICDE
2011
IEEE
14 years 4 months ago
2011
IEEE
Abstract—MapReduce is emerging as a generic parallel programming paradigm for large clusters of machines. This trend combined with the growing need to run machine learning (ML) a...