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» Design, Implementation and Performance Evaluation of IP-VPN
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CGO
2005
IEEE
15 years 4 months ago
SWIFT: Software Implemented Fault Tolerance
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
George A. Reis, Jonathan Chang, Neil Vachharajani,...
IUI
2012
ACM
13 years 6 months ago
1F: one accessory feature design for gesture recognizers
One Feature (1F) is a simple and intuitive pruning strategy that reduces considerably the amount of computations required by Nearest-Neighbor gesture classifiers while still pres...
Radu-Daniel Vatavu
CHI
2011
ACM
14 years 2 months ago
MOGCLASS: evaluation of a collaborative system of mobile devices for classroom music education of young children
Composition, listening, and performance are essential activities in classroom music education, yet conventional music classes impose unnecessary limitations on students’ ability...
Yinsheng Zhou, Graham Percival, Xinxi Wang, Ye Wan...
86
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HRI
2009
ACM
15 years 6 months ago
Robot motivator: improving user performance on a physical/mental task
We describe the design and implementation of a socially assistive robot that is able to monitor the performance of a user during a combined mental and physical task, with the purp...
Juan Fasola, Maja J. Mataric
DSD
2009
IEEE
145views Hardware» more  DSD 2009»
15 years 5 months ago
High Performance Image Processing on a Massively Parallel Processor Array
Multicore and manycore processors are the new wave of computing, offering high performance by using large numbers of simple processors. In this paper, we describe the implementati...
Roberto R. Osorio, Cesar Diaz-Resco, Javier D. Bru...