Sciweavers

200 search results - page 10 / 40
» Design, Implementation and Performance of a Content-Based Sw...
Sort
View
88
Voted
ICNP
2003
IEEE
15 years 5 months ago
Stress Resistant Scheduling Algorithms for CIOQ Switches
Practical crossbar scheduling algorithms for CIOQ switches such as PIM and ¢ -SLIP, can perform poorly under extreme traffic conditions, frequently failing to be workconserving....
Prashanth Pappu, Jonathan S. Turner
102
Voted
ICCAD
1996
IEEE
140views Hardware» more  ICCAD 1996»
15 years 4 months ago
Register-transfer level estimation techniques for switching activity and power consumption
We present techniques for estimating switching activity and power consumption in register-transfer level (RTL) circuits. Previous work on this topic has ignored the presence of gl...
Anand Raghunathan, Sujit Dey, Niraj K. Jha
FPGA
2006
ACM
90views FPGA» more  FPGA 2006»
15 years 4 months ago
Improving performance and robustness of domain-specific CPLDs
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
Mark Holland, Scott Hauck
102
Voted
ANCS
2007
ACM
15 years 4 months ago
Optimal packet scheduling in output-buffered optical switches with limited-range wavelength conversion
All-optical packet switching is a promising candidate for future high-speed switching. However, due to the absence of optical Random Access Memory, the traditional Virtual Output ...
Lin Liu, Yuanyuan Yang
ANCS
2007
ACM
15 years 4 months ago
Low-latency scheduling in large switches
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short...
Wladek Olesinski, Nils Gura, Hans Eberle, Andres M...