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ACSC
2005
IEEE
15 years 6 months ago
A High Performance Kernel-Less Operating System Architecture
Operating Systems provide services that are accessed by processes via mechanisms that involve a ring transition to transfer control to the kernel where the required function is pe...
Amit Vasudevan, Ramesh Yerraballi, Ashish Chawla
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
15 years 6 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
130
Voted
CNSR
2010
IEEE
164views Communications» more  CNSR 2010»
15 years 3 months ago
Buffered Crossbar Fabrics Based on Networks on Chip
— Buffered crossbar (CICQ) switches have shown a high potential in scaling Internet routers capacity. However, they require expensive on-chip buffers whose cost grows quadratical...
Lotfi Mhamdi, Kees Goossens, Iria Varela Senin
139
Voted
SIGCOMM
2009
ACM
15 years 7 months ago
BCube: a high performance, server-centric network architecture for modular data centers
This paper presents BCube, a new network architecture specifically designed for shipping-container based, modular data centers. At the core of the BCube architecture is its serve...
Chuanxiong Guo, Guohan Lu, Dan Li, Haitao Wu, Xuan...
85
Voted
VLSID
2005
IEEE
149views VLSI» more  VLSID 2005»
16 years 25 days ago
ADOPT: An Approach to Activity Based Delay Optimization
: The direct result of shrinking devices is not only higher densities but also increased switching activity and thus higher device temperatures. The variation in temperature over t...
Gaurav Arora, Abhishek Sharma, D. Nagchoudhuri, M....