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97
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ARC
2007
Springer
116views Hardware» more  ARC 2007»
15 years 6 months ago
Systematic Customization of On-Chip Crossbar Interconnects
Abstract. In this paper, we present a systematic design and implementation of reconfigurable interconnects on demand. The proposed on-chip interconnection network provides identic...
Jae Young Hur, Todor Stefanov, Stephan Wong, Stama...
TPDS
2002
105views more  TPDS 2002»
15 years 2 days ago
HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
Multiprocessor architectures demand efficient interprocessor communication to maximize system utilization and performance. To meet future demands, these interconnects must communic...
Phil May, Santithorn Bunchua, D. Scott Wills
RTSS
2006
IEEE
15 years 6 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
100
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ANCS
2007
ACM
15 years 4 months ago
Experimenting with buffer sizes in routers
Recent theoretical results in buffer sizing research suggest that core Internet routers can achieve high link utilization, if they are capable of storing only a handful of packets...
Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McK...
GLVLSI
2008
IEEE
197views VLSI» more  GLVLSI 2008»
15 years 17 days ago
Efficient tree topology for FPGA interconnect network
This paper presents an improved Tree-based architecture that unifies two unidirectional programmable networks: A predictible downward network based on the Butterfly-FatTree topolo...
Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib ...