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ICNP
1998
IEEE
15 years 4 months ago
Distributed Packet Rewriting and its Application to Scalable Server Architectures
To construct high performance Web servers, system builders are increasingly turning to distributed designs. An important challenge that arises in such designs is the need to direc...
Azer Bestavros, Mark Crovella, Jun Liu, David Mart...
77
Voted
UIST
2005
ACM
15 years 6 months ago
DT controls: adding identity to physical interfaces
In this paper, we show how traditional physical interface components such as switches, levers, knobs and touch screens can be easily modified to identify who is activating each co...
Paul H. Dietz, Bret Harsham, Clifton Forlines, Dar...
97
Voted
ISMVL
2010
IEEE
174views Hardware» more  ISMVL 2010»
15 years 5 months ago
Quaternary Voltage-Mode Logic Cells and Fixed-Point Multiplication Circuits
—Fixed-point multiplication architectures are designed and evaluated using a set of logic cells based on a radix-4, quaternary number system. The library of logic circuits is bas...
Satyendra R. Datla, Mitchell A. Thornton
154
Voted
ANCS
2005
ACM
15 years 6 months ago
Gigabit routing on a software-exposed tiled-microprocessor
This paper investigates the suitability of emerging tiled-architectures, equipped with low-latency on-chip networks, for high-performance network routing. In this paper, we presen...
Umar Saif, James W. Anderson, Anthony Degangi, Ana...
SIGCOMM
2010
ACM
15 years 19 days ago
PacketShader: a GPU-accelerated software router
We present PacketShader, a high-performance software router framework for general packet processing with Graphics Processing Unit (GPU) acceleration. PacketShader exploits the mas...
Sangjin Han, Keon Jang, KyoungSoo Park, Sue B. Moo...