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ICC
2008
IEEE
118views Communications» more  ICC 2008»
15 years 4 months ago
A Distributed Scheduling Algorithm for an Optical Switching Fabric
— Designing switching architectures for network routers and switches needs to consider limits imposed by the electronic technology, like small bandwidth×distance factors, power ...
Andrea Bianco, Elisabetta Carta, Davide Cuda, Jorg...
86
Voted
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
15 years 7 months ago
Design and Implementation of Scalable Low-Power Montgomery Multiplier
In this paper, an efficient Montgomery multiplier is introduced for the modular exponentiation operation, which is fundamental to numerous public-key cryptosystems. Four aspects a...
Hee-Kwan Son, Sang-Geun Oh
76
Voted
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 2 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
13 years 10 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...
84
Voted
GLOBECOM
2007
IEEE
15 years 4 months ago
GMPLS-Based Hybrid 1+N Link Protection Over p-Cycles: Design and Performance
—In [1], the author introduced a strategy to use network coding on p-Cycles in order to provide 1+N protection for straddling connections and links against single link failures i...
Ahmed E. Kamal