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» Design Challenges for High Performance Nano-Technology
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RTAS
1997
IEEE
15 years 1 months ago
Scalable Hardware Priority Queue Architectures for High-Speed Packet Switches
ÐWith effective packet-scheduling mechanisms, modern integrated networks can support the diverse quality-of-service requirements of emerging applications. However, arbitrating bet...
Sung-Whan Moon, Kang G. Shin, Jennifer Rexford
SECON
2008
IEEE
15 years 3 months ago
A Multi-AP Architecture for High-Density WLANs: Protocol Design and Experimental Evaluation
—Fast proliferation of IEEE 802.11 wireless devices has led to the emergence of High-Density (HD) Wireless Local Area Networks (WLANs), where it is challenging to improve the thr...
Yanfeng Zhu, Zhisheng Niu, Qian Zhang, Bo Tan, Zhi...
VRST
2005
ACM
15 years 3 months ago
Real time tracking of high speed movements in the context of a table tennis application
In this paper we summarize the experiences we made with the implementation of a table tennis application. After describing the hardware necessities of our system we give insight i...
Stephan Rusdorf, Guido Brunnett
JPDC
2007
84views more  JPDC 2007»
14 years 9 months ago
Performance of memory reclamation for lockless synchronization
Achieving high performance for concurrent applications on modern multiprocessors remains challenging. Many programmers avoid locking to improve performance, while others replace l...
Thomas E. Hart, Paul E. McKenney, Angela Demke Bro...
AIED
2005
Springer
15 years 3 months ago
Motivating Appropriate Challenges in a Reciprocal Tutoring System
Abstract. Formalizing a student model for an educational system requires an engineering effort that is highly domain-specific. This model-specificity limits the ability to scale ...
Ari Bader-Natal, Jordan B. Pollack