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» Design Challenges for High Performance Nano-Technology
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ICCAD
2005
IEEE
123views Hardware» more  ICCAD 2005»
15 years 6 months ago
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
Abstract— Physics offers several active devices with nanometerscale footprint, which can be best used in combination with a CMOS subsystem. Such hybrid circuits offer the potenti...
André DeHon, Konstantin Likharev
MICRO
2006
IEEE
132views Hardware» more  MICRO 2006»
15 years 3 months ago
Scalable Cache Miss Handling for High Memory-Level Parallelism
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
James Tuck, Luis Ceze, Josep Torrellas
ICRA
2006
IEEE
82views Robotics» more  ICRA 2006»
15 years 3 months ago
Highly Articulated Robotic Probe for Minimally Invasive Surgery
- We have developed a novel highly articulated robotic probe (HARP) that can thread through tightly packed volumes without disturbing the surrounding tissues and organs. We use car...
Amir Degani, Howie Choset, Alon Wolf, Marco A. Zen...
95
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SBCCI
2005
ACM
122views VLSI» more  SBCCI 2005»
15 years 3 months ago
Phase noise performances of a cross-coupled CMOS VCO with resistor tail biasing
The Voltage Controlled Oscillator (VCO) is a fundamental block in RF IC architectures. Today’s wireless communication applications do require a high level of performances from s...
Sergio Gagliolo, Giacomo Pruzzo, Daniele D. Cavigl...
ADHOC
2007
108views more  ADHOC 2007»
14 years 9 months ago
Hop-distance based addressing and routing for dense sensor networks without location information
One of the most challenging problems in wireless sensor networks is the design of scalable and efficient routing algorithms without location information. The use of specialized ha...
Serdar Vural, Eylem Ekici