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» Design Challenges for High Performance Nano-Technology
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ICCD
2006
IEEE
132views Hardware» more  ICCD 2006»
15 years 6 months ago
FPGA-based Design of a Large Moduli Multiplier for Public Key Cryptographic Systems
— High secure cryptographic systems require large bit-length encryption keys which presents a challenge to their efficient hardware implementation especially in embedded devices...
Osama Al-Khaleel, Christos A. Papachristou, Franci...
ASPDAC
2008
ACM
154views Hardware» more  ASPDAC 2008»
14 years 11 months ago
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching
Meeting power and performance requirement is a challenging task in high speed ALUs. Supply voltage scaling is promising because it reduces both switching and active power but it al...
Swaroop Ghosh, Kaushik Roy
IEEEPACT
2009
IEEE
14 years 7 months ago
Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor
Efficiently using the hardware capabilities of the Cell processor, a heterogeneous chip multiprocessor that uses several levels of parallelism to deliver high performance, and bei...
Tarik Saidani, Joel Falcou, Claude Tadonki, Lionel...
ISJGP
2007
146views more  ISJGP 2007»
14 years 9 months ago
End-to-End Security Across Wired-Wireless Networks for Mobile Users
Abstract  Recent advances in mobile computing and wireless communication technologies are enabling high mobility and flexibility of anytime, anywhere service access for mobile us...
Sherali Zeadally, Nicolas Sklavos, Moganakrishnan ...
ANTSW
2006
Springer
15 years 1 months ago
An Analysis of the Different Components of the AntHocNet Routing Algorithm
Abstract. Mobile ad hoc networks are a class of highly dynamic networks. In previous work, we developed a new routing algorithm, called AntHocNet, for these challenging network env...
Frederick Ducatelle, Gianni Di Caro, Luca Maria Ga...